The scaling of semiconductor devices, such as dynamic random access memory (DRAM), logic devices, and the like, may be limited by gate leakage (Jg). For example, as thickness of a gate dielectric layer is scaled, current may leak between the channel and the gate of a transistor device causing device failure. The gate leakage may be reduced by incorporating nitrogen into the gate dielectric layer. For example, a gate dielectric layer at the 32 nm node may comprise silicon oxynitride (SiON), where the presence of nitrogen reduces gate leakage in the device.
Typically, nitrogen is incorporated into the gate dielectric layer by a plasma nitridation process that provides for gate leakage reduction at the expense of other desired properties, for example, flat band voltage (Vfb), threshold voltage (Vt), and mobility. For example, increased nitrogen content in the gate dielectric layer may undesirably increase Vt and excessively decrease mobility. Further, oxygen may diffuse from the gate dielectric layer under typical processing conditions, thus further reducing device performance, for example by degrading the dielectric properties of the gate dielectric layer.
Accordingly, there is need in the art for a method of forming gate dielectric layers having reduced gate leakage at smaller device nodes without reducing device performance.